View SCF5250DAG1201_7622898.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? freescale semiconductor, inc., 2006. all rights reserved. freescale semiconductor data sheet: technical data this document contains information on a product under developm ent. freescale reserves the right to change or discontinue this product without notice. document number: scf5250ec rev. 1.3 , 07/2006 scf5250 package information mapbga?196 lqfp-144 ordering information: see table 1 on page 2 1 introduction this document provides an overview of the scf5250 coldfire ? processor and general descriptions of scf5250 features and its various modules. the scf5250 was designed as a system controller/decoder for compressed audio music players, especially portable and auto motive cd and hard disk drive players. the 32-bit coldfire core with enhanced multiply accumulate (emac) unit provides optimum performance and code density for the combination of control code and signal pr ocessing required for audio decoding and post processi ng, file management, and system control. low power features include a hardwired cd rom decoder, advanced 0.13um cmos process technology, 1.2v core power supply, a nd on-chip 128kbyte sram that enables windows media audio (wma) decoding without the need for external dram in cd applications. the scf5250 is also an excellent general purpose system controller with over 110 dhrystone 2.1 mips @ 120mhz performance at a very competitive price. the scf5250 integrated coldfire? microprocessor data sheet contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 scf5250 block diagram . . . . . . . . . . . . . . . . 8 3 signal descriptions . . . . . . . . . . . . . . . . . . . . 8 4 electrical characteristics . . . . . . . . . . . . . . 21 5 pin-out and package information . . . . . . . . 36 6 product documentation . . . . . . . . . . . . . . . . 55
scf5250 data sheet: technical data , rev. 1.3 2 freescale semiconductor integrated peripherals and enhan ced mac unit allow the scf5250 to re place both the microcontroller and the dsp in certain applications. mo st peripheral pins can also be re mapped as general purpose i/o pins. 1.1 orderable part numbers table 1 lists the orderable part num bers for the scf5250 processor. 1.2 scf5250 features this section provides brief de scriptions of the features of the scf5250 processor. 1.2.1 coldfire v2 core the coldfire processor version 2 core consists of two independent, decoupled pipeline structures to maximize performance while minimizi ng core size.the instruction fetc h pipeline (ifp) is a two-stage pipeline for prefetching instructions . the prefetched instruction stream is then gated into the two-stage operand execution pipeline (oep), whic h decodes the instruction, fetches the required operands, and then executes the required function. because the ifp and oep pipelines are decoupled by an instruction buffer that serves as a fifo queue, the ifp can prefetch in structions in advance of their actual use by the oep, which minimizes time stalled waiting for instructions . the oep is implemented in a two-stage pipeline featuring a traditional risc data path with a dual-read -ported register file feed ing an arithmetic/logic unit (alu). table 1. orderable part numbers orderable part number maximum clock frequency package type operating temperature range part status scf5250lpv100 100 mhz 144 pin qfp -20 c to 70 c leaded scf5250lag100 100 mhz 144 pin qfp -20 c to 70 c lead free scf5250pv120 120 mhz 144 pin qfp -20 c to 70 c leaded scf5250ag120 120 mhz 144 pin qfp -20 c to 70 c lead free scf5250dag120 1 1 scf5250dag120?this device has the same feature set, pi n assignment and specification as scf5250ag120 with the addition of including the cost of the mp3 decoder royalty to be paid to thomson licensing s.a. for use of the mp3 patent rights described at http://mp3licensing.com/patents/index.html . 120 mhz 144 pin qfp -20 c to 70 c lead free scf5250eag120 2 2 scf5250eag120?this device has the same feature set, pin assignment and specificat ion as scf5250ag120 with the addition of including the cost of the mp3 encoder and decoder ro yalty to be paid to thomson licensing s.a. for use of the mp3 patent rights described at http://mp3licensing.co m/patents/index.html. 120 mhz 144 pin qfp -20 c to 70 c lead free scf5250cpv120 120 mhz 144 pin qfp -40 c to 85 c leaded scf5250cag120 120 mhz 144 pin qfp -40 c to 85 c lead free scf5250vm120 120 mhz 196 ball mapbga -20 c to 70 c lead free
scf5250 data sheet: technical data , rev. 1.3 freescale semiconductor 3 1.2.2 dma controller the scf5250 provides four fully programmable dma channels for quick data transfer. single and dual address mode is supported with th e ability to program bursting and cycle stealing. data transfer is selectable as 8, 16, 32, or 128-bits . packing and unpacking is supported. two internal audio channels and the dual uart can be used with the dma channels. all channels can perform memory to memory transfers. the dma controller has a user-sel ectable, 24- or 16-bit counter and a programmable dma exception handler. external requests are not supported. 1.2.3 enhanced multiply and accumulate module (emac) the integrated emac unit provides a common set of dsp operations and enhances the integer multiply instructions in the coldfire architecture. the em ac provides functionality in three related areas: 1. faster signed and unsigned integer multiplies 2. new multiply-accumulate operations supporting signed and unsigned operands 3. new miscellaneous register operations multiplies of 16x16 and 32x32 wi th 48-bit accumulates are supported in addition to a full set of extensions for signed and unsigned integers pl us signed, fixed-point fractional input operands. the emac has a single-clock issue for 32x32-bit multiplication inst ructions and implements a four-stage execution pipeline. 1.2.4 instruction cache the instruction cache impr oves system performance by providing cached instructi ons to the execution unit in a single clock. the scf5250 proce ssor uses a 8k-byte, di rect-mapped instructi on cache to achieve 107 mips at 120 mhz. the cache is accesse d by physical addresses, where each 16-byte line consists of an address tag and a valid bit. the inst ruction cache also includes a burstin g interface for 16-bit and 8-bit port sizes to quickly fill cache lines. 1.2.5 internal 128-kbyte sram the 128-kbyte on-chip sram is available in two banks, sram0 (64k) and sr am1 (64k). it provides one clock-cycle access for the coldfire core. this sr am can store processor stack and critical code or data segments to maximize performance. memory in sr am1 can be accessed under dma. 1.2.6 sdram controller the scf5250 sdram controller provides a glueless interface for one bank of sdram up to 32 mb (256 mbits). the controller supports a 16-bit data bus . a unique addressing scheme allows for increases in system memory size without rer outing address lines and rewiring boa rds. the controller operates in page mode, non-page mode, and burst -page mode and supports sdrams.
scf5250 data sheet: technical data , rev. 1.3 4 freescale semiconductor 1.2.7 system interface the scf5250 provides a glueless inte rface to 16-bit port si ze sram, rom, and peri pheral devices with independent programmable c ontrol of the assertion and negation of chip-select and write-enable signals. the scf5250 also supports bursting roms. 1.2.8 external bus interface the bus interface controller transfers informati on between the coldfire core or dma and memory, peripherals, or other device s on the external bus. the external bus in terface provides 23 bits of address bus space, a 16-bit data bus, output enable, and read/write signals. this interface implements an extended synchronous protocol that supports bursting operations. 1.2.9 serial audio interfaces the sc5250 digital audio interface provi des three serial philips iis/sony eiaj interfaces. one interface is a 4-pin (1 bit clock, 1 word clock, 1 data in, 1 data out), the other two interfaces are 3-pin (1 bit clock, 1 word clock, 1 data in or out). the serial in terfaces have no limit on minimum sampling frequency. maximum sampling frequency is determined by maxi mum frequency on bit clock input. this is 1/3 the frequency of the internal system clock. 1.2.10 iec958 digital audio interfaces the scf5250 has one digital audio i nput interface, and one digital a udio output interface. the single output carries the consumer ?c? channel. 1.2.11 audio bus the audio interfaces connect to an inte rnal bus that carries all audio data. each receiver places its received data on the audio bus and eac h transmitter takes data from the audi o bus for transmission. each transmitter has a source select register. in addition to the audio interfaces, there are six cpu accessi ble registers connected to the audio bus. three of these registers allow data reads from the audio bus and allow select ion of the audio source. the other three register provide a write path to the audio bus and can be selected by transmitters as the audio source. through these registers, the cpu has acces s to the audio samples for processing. audio can be routed from a receiver to a transmitte r without the data being processed by the core so the audio bus can be used as a digital audio data switc h. the audio bus can also be used for audio format conversion. 1.2.12 cd-rom encoder/decoder the scf5250 is capable of proce ssing cd-rom sectors in hardware . processing is compliant with cd-rom and cd-rom xa standards.
scf5250 data sheet: technical data , rev. 1.3 freescale semiconductor 5 the cd-rom decoder performs fo llowing functions in hardware: ? sector sync recognition ? descrambling of sectors ? verification of the crc checksum for mode 1, mode 2 form 1, and mode 2 form 2 sectors ? third-layer error corr ection is not performed the cd-rom encoder performs fo llowing functions in hardware: ? sector sync recognition ? scrambling of sectors ? insertion of the crc checksum for mode 1, mode 2 form 1, and mode 2 form 2 sectors. ? third-layer error encoding needs to be done in software. this can use approximately 5?10 mhz of performance for single-speed. 1.2.13 dual uart module two full-duplex uarts with independent receive and tr ansmit buffers are in this module. data formats can be 5, 6, 7, or 8 bits with even, odd, or no parity , and up to 2 stop bits in 1/16 increments. four-byte receive buffers and two-byte transm it buffers minimize cpu service calls. the dual uart module also provides several error-detection and maskable-i nterrupt capabilities. modem support includes request-to-send (rts ) and clear-to-send (cts ) lines. the system clock provides the clocking function from a programmable prescaler . you can select full duplex, auto-echo loopback, local loopback, and remote loopback modes. the programmable dual uarts can interrupt the cpu on various normal or error-condition events. 1.2.14 queued serial peripheral interface qspi the qspi module provides a serial pe ripheral interface with queued tran sfer capability. it supports up to 16 stacked transfers at a time, making cpu interventi on between transfers unnecess ary. transfers of up to 15 mbits/second are possible at a cpu clock of 120 mhz. the qspi supp orts master mode operation only. 1.2.15 timer module the timer module includes tw o general-purpose timers, e ach of which contains a free-running 16-bit timer. timer0 has an external pin tout0, which can be used in output compare mode. this mode triggers an external signal or interrupt s the cpu when the timer re aches a set value, and can also generate waveforms on tout0. the timer unit has an 8-bit prescaler that allows programming of the clock input frequency, which is derived from the system clock. in a ddition to the 1 and 16 clock deri ved from the bus clock (cpu clock / 2), the programmable timer-output pins either generate an activ e-low pulse or toggle the outputs.
scf5250 data sheet: technical data , rev. 1.3 6 freescale semiconductor 1.2.16 ide and smartmedia interfaces the scf5250 system bus allows connection of an ide ha rd disk drive or smartmedia flash card with a minimum of external hardware. the external hardware consists of bus buffers fo r address and data and are intended to reduce the load on the bus and prevent sdram and flash accesses to propagate to the ide bus. the control si gnals for the buffers are generated in the scf5250. low cost version scf5250lpv100 and scf5250l ag100 does not run production test for the ide/cf/sd/mmc interfaces. free scale does not guarantee these interfaces will work on these two devices. 1.2.17 analog/digital converter (adc) the six channel adc is a based on the sigma-delta concept with 12- bit resolution. both the analogue comparator and digital s ections of the adc are provided internal ly. an external integrator circuit (resistor/capacitor) is required, which is driven by the adc output. a software inte rrupt is provided when the adc measurement cycle is complete. 1.2.18 i 2 c module the two-wire i 2 c bus interface, which is compliant with the philips i 2 c bus standard, is a bidirectional serial bus that exchanges data between devices. the i 2 c bus minimizes the interconnection between devices in the end system and is best suited for applications that need occasional bursts of rapid communication over short distances among several devices. bus cap acitance and the number of unique addresses limit the maximum communication length a nd the number of devices that can be connected. 1.2.19 chip-selects up to four programmable chip-select outputs provide signals that enable glueless connection to external memory and peripheral circuits. the base address, access permissions a nd automatic wait-state insertion are programmable with configurat ion registers. these signals al so interface to 16-bit ports. cs0 is active after reset to provide boot-up from external flash/rom. 1.2.20 gpio interface a total of 60 general purpose input s and 57 general purpose outputs are available. these are multiplexed with various other signals. seven of the gpio i nputs have edge sensitive interrupt capability. 1.2.21 interrupt controller the interrupt controller provides user-programmable control of a to tal of 57 interrupts. there are 49 internal interrupt sources. in add ition, there are 7 gpios where interrupts can be generated on the rising or falling edge of the pin. all interrupts are au tovectored and interrupt levels are programmable.
scf5250 data sheet: technical data , rev. 1.3 freescale semiconductor 7 1.2.22 jtag to help with system diagnostics and manufac turing testing, the scf 5250 includes dedicated user-accessible test logic that co mplies with the ieee 1149.1a standard for boundary scan testability, often referred to as joint test action group, or jt ag. for more information, refer to the ieee 1149.1a standard. freescale provides bsdl files for jtag testing. 1.2.23 system debug interface the coldfire processor core debug interface s upports real-time instruct ion trace and debug, plus background-debug mode. a background-debug mode (bdm) interface provides system debug. in real-time instruction tra ce, four status lines provide information on processor activity in real time (pst pins). a four-bit wide debug data bus (ddata) displays operand data and change-of-flow addresses, which helps track the machin e?s dynamic execution path. 1.2.24 crystal and on-chip pll typically, an external 16.92 mhz or 33.86 mhz clock input is used for cd r/w applications, while an 11.2896 mhz clock is more practical for portable cd player applications. however, the on-chip programmable pll, which generates the processor clock, allows the use of almost any low frequency external clock (5-35 mhz). two clock outputs (mclk1 and mc lk2) are provided for use as audio master clock. the output frequencies of both outputs are progra mmable to fxtal, fxtal/2, fxtal/3, and fxtal/4. the fx tal/3 option is only available when the 33.86 mhz crystal is connected. the scf5250 supports vco operation of the oscillator by means of a 16-bit pulse density modulation output. using this mode, it is possibl e to lock the oscillator to the fr equency of an incoming iec958 or iis signal. the maximum trim de pends on the type and design of the osci llator. typically a trim of +/- 100 ppm can be achieved with a crystal oscillator and over +/- 1000 ppm with an lc oscillator. 1.2.25 boot rom the boot rom on the scf5250 serves to boot the cpu in designs which do not have external flash memory or rom. typically this occurs in systems which have a separate mcu to control the system, and/or the scf5250 is used as a stand-alone decoder. the scf5250 can be booted in one of three modes: ? external rom ? internal rom master mode ? boots from i2c, spi, or ide ? internal rom slave mode ? boots from i2c or uart 1.2.26 voltage regulator the scf5250 contains an on-chip line ar regulator that generates 1.2v fr om a 3.3v input. the regulator is self-contained and drives th e 1.2v core voltage out on on e pin that can be used to power the core supply
scf5250 data sheet: technical data , rev. 1.3 8 freescale semiconductor pins at the board level. in battery powered portable appl ications, it is recommende d that an external dc-dc converter be used to generate the 1.2v co re voltage to minimi ze power consumption. 2 scf5250 block diagram figure 1 illustrates the functional block diagram of the scf5250 processor. figure 1. scf5250 block diagram 3 signal descriptions this section describes the scf5250 processor?s input and output signals. the sign al descriptions shown in table 2 are grouped according to relevant functionality. emac v2 coldfire ? core system bus controller sdram ctr & chip selects qspi i 2 c x2 dmas / timers jtag 12-bit adc ide interface gpi/o pll bdm 128k sram 8k i-cache flash media int boot rom oscillator cd rom block encode & decode i 2 s rx x3 i 2 s tx x2 uart x2 spdif tx spdif rx 1.2v regulator
scf5250 data sheet: technical data , rev. 1.3 freescale semiconductor 9 table 2. scf5250 signal index signal name mnemonic function input/ output reset state address a[24:1] a[23]/gpo54 24 address lines, address line 23 multiplexed with gpo54 and address 24 is multiplexed with a20 (sdram access only). out x read-write control r/w bus write enable - indicates if read or write cycle in progress out h output enable oe output enable for asynchronous memories connected to chip selects out negated data d[31:16] data bus used to transfer word data in/out hi-z synchronous row address strobe sdras /gpio59 row address strobe for external sdram. out negated synchronous column address strobe sdcas /gpio39 column address strobe for external sdram out negated sdram write enable sdwe /gpio38 write enable for external sdram out negated sdram upper byte enable sdudqm /gpo53 indicates during writ e cycle if high byte is written out ? sdram lower byte enable sdldqm /gpo52 indicates during writ e cycle if low byte is written out ? sdram chip selects sd_cs0 /gpio60 sdram chip select in/out negated sdram clock enable bclke/gpio63 sdram clock enable out ? system clock bclk/gpio40 s dram clock output in/out ? isa bus read strobe ide-dior /gpio31 (cs2) there is 1 isa bus read strobe and 1 isa bus write strobe. they allow connection of one independent isa bus peripherals, e.g. an ide slave device. in/out ? isa bus write strobe ide-diow /gpio32 (cs2) in/out ? isa bus wait signal ide-iordy /gpio33 isa bus wait line - available for both busses in/out ? chip selects[2:0] cs0 /cs4 cs1 /qspi_cs3/gpio28 enables peripherals at programmed addresses. cs[ 0] provides boot rom selection out in/out negated buffer enable 1 bufenb1 /gpio29 two programmable buffer enables allow seamless steering of external buffers to split data and address bus in sections. in/out ? buffer enable 2 bufenb2 /gpio30 in/out ? transfer acknowledge ta /gpio12 transfer acknowledge signal in/out ? wake up wake_up /gpio21 wake-up signal input in ? serial clock line sc l0/sdata1_bs1/gpio41 scl1/txd1/gpio10 clock signal for dual i 2 c module operation in/out ? serial data line sda0/sdata3/gpio42 sda1/rxd1/gpio44 serial data port for second i 2 c module operation in/out ? receive data sda1/rxd1/gpio44 rxd0/gpio46 signal is receive serial data input for duart in ?
scf5250 data sheet: technical data , rev. 1.3 10 freescale semiconductor transmit data scl1/txd1/gpio10 txd0/gpio45 signal is transmit serial data output for duart out ? request-to-send ddata3/rts0 /gpio4 ddata1/rts1 /sdata2_bs2/gpio2 duart signals a ready to receive data query out ? clear-to-send ddata2/ctso /gpio3 ddata0/cts1 /sdata0_sdio1/gpio1 signals to duart that data can be transmitted to peripheral in ? timer output sdatao1/tout0/gpio18 capa ble of output waveform or pulse generation out ? iec958 inputs ebuin1/gpio36 ebuin2/sclk_out/gpio13 ebuin3/cmd_sdio2/gpio14 qspi_cs0/ebuin4/gpio15 audio interfaces iec958 inputs in ? iec958 outputs ebuout1/gpio37 qspi_cs1/ebuout2/gpio16 audio interfaces iec958 outputs out ? serial data in sdatai1/gpio17 sdatai3/gpio8 audio interfaces serial data inputs in ? serial data out sdatao1/tout0/gpio18 sdatao2/gpio34 audio interfaces serial data outputs in/out out ? word clock lrck1/gpio19 lrck2/gpio23 lrck3/gpio43/audio_clock audio interfaces serial word clocks in/out ? bit clock sclk1/gpio20 sclk2/gpio22 sclk3/gpio35 audio interfaces serial bit clocks in/out ? serial input ef/gpio6 error flag serial in in/out ? serial input cflg/gpio5 c-flag serial in in/out ? subcode clock rck/qspi_din/qspi_dout/ gpio26 audio interfaces subcode clock in/out ? subcode sync qspi_dout/sfsy/gpio27 audio interfaces subcode sync in/out ? subcode data qspi_clk/subr/gpio25 aud io interfaces subcode data in/out ? clock frequency trim xtrim/gpio0 clock trim control out ? audio clocks out mclk1/gpio11 qspi_cs2/mclk2/gpio24 dac output clocks out ? audio clock in lrck3/gpio43/audio_clock optional audio clock input ? ? table 2. scf5250 signal index (continued) signal name mnemonic function input/ output reset state
scf5250 data sheet: technical data , rev. 1.3 freescale semiconductor 11 memory stick/ secure digital interface ebuin3/cmd_sdio2/gpio14 secure digital command lane memory stick interface 2 data i/o in/out ? ebuin2/sclk_out/gpio13 clock out for both memory stick interfaces and for secure digital in/out ? ddata0/cts1 /sdata0_sdio1/gpio1 secure dig ital serial data bit 0 memory stick interface 1 data i/o in/out ? scl0/sdata1_bs1/gpio41 secure digital serial data bit 1 memory stick interface 1 strobe in/out ? ddata1/rts1 /sdata2_bs2/gpio2 secure digit al serial data bit 2 memory stick interface 2 strobe reset output signal in/out ? sda0/sdata3/gpio42 secure digit al serial data bit 3 in/out ? adc in adin0/gpi52 adin1/gpi53 adin2/gpi54 adin3/gpi55 adin4/gpi56 adin5/gpi57 analog to digital converter input signals in ? adc out adref adout/sclk4/gpio58 analog to digital convertor output signal. connect to adref via integrator network. in/out ? qspi clock qspi_clk/subr/gpio 25 qspi clock signal in/out ? qspi data in rck/qspi _din/qspi_dout/gpio26 qspi data input in/out ? qspi data out rck/qspi_din/qspi_dout/gpio26 qspi_dout/sfsy/gpio27 qspi data out in/out ? qspi chip selects q spi_cs0/ebuin4/gpio15 qspi_cs1/ebuout2/gpio16 qspi_cs2/mclk2/gpio24 cs1 /qspi_cs3/gpio28 qspi chip selects in/out ? crystal in crin crystal input in ? crystal out crout crystal out out ? reset in rsti proce ssor reset input in ? freescale test mode test[2:0] test pins. in ? linear regulator output linout outputs 1.2 v to supply core out ? linear regulator input linin input, typically i/o supply (3.3v) in ? linear regulator ground lingnd ? ? ? high impedance hi-z assertion tri-st ates all output signal pins. in ? debug data ddata0/cts1 /sdata0_sdio1/gpio1 ddata1/rts1 /sdata2_bs2/gpio2 ddata2/cts0 /gpio3 ddata3/rts0 /gpio4 displays captured processor data and break-point status. in/out hi-z table 2. scf5250 signal index (continued) signal name mnemonic function input/ output reset state
scf5250 data sheet: technical data , rev. 1.3 12 freescale semiconductor 3.1 gpio many pins have an optional gpio function. ? general purpose input is always ac tive, regardless of state of pin. ? general purpose output or primar y output is determined by the appropriate setting of the pin multiplex control registers, gpio-funct ion, gpio1-function and pin-config. ? at power-on reset, all pins ar e set to their primary function. 3.2 scf5250 bus signals these signals provide the external bus interface to the scf5250 processor. 3.2.1 address bus ? the address bus provides the addr ess of the byte or most significa nt byte of the word or longword being transferred. the address li nes also serve as the dram addr ess pins, providing multiplexed row and column address signals. ? bits 23 down to 1 and 24 of the a ddress are available. a24 is inte nded to be used with 256 mbit dram?s. signals are named: ? a[23:1] ? a20/24 processor status pst0/gpio50 pst1/gpio49 pst2/intmon2/gpio48 pst3/intmon1/gpio47 indicates internal processor status. in/out hi-z processor clock pstclk/gpio51 processor clock output out ? test clock tck clock signal for ieee 1149.1a jtag. in ? test reset/development serial clock trst /dsclk multiplexed signal that is asynchronous reset for jtag controller. clock input for debug module. in ? test mode select/ break point tms/bkpt multiplexed signal that is test mode select in jtag mode and a hardware break-point in debug mode. in ? test data input / development serial input tdi/dsi multiplexed serial input for the jtag or background debug module. in ? test data output/development serial output tdo/dso multiplexed serial output for the jtag or background debug module. out ? table 2. scf5250 signal index (continued) signal name mnemonic function input/ output reset state
scf5250 data sheet: technical data , rev. 1.3 freescale semiconductor 13 3.2.2 read-write control this signal indicates during any bus cycle whether a read or write is in progress. a low is write cycle and a high is a read cycle. 3.2.3 output enable the oe signal is intended to be connected to the out put enable of asynchronous memories connected to chip selects. during bus read cycles, the coldfire processor will drive oe low. 3.2.4 data bus the data bus (d[31:16]) is bi-dir ectional and non-multiplexed. data is registered by the scf5250 on the rising clock edge. the data bus uses a default conf iguration if none of the chip-selects or dram bank match the address decode. al l 16 bits of the data bus are driven during writes, re gardless of port width or operand size. 3.2.5 transfer acknowledge the ta /gpio12 pin is the transfer acknowledge signal. 3.3 sdram controller signals the following sdram signals provide a glueless interface to external sdram. an sdram width of 16 bits is supported and can access as much as 32mb of memory. adrams are not supported. table 3. sdram controller signals sdram signal description synchronous dram row address strobe the sdras /gpio59 active low pin provides a s eamless interface to the ras input on synchronous dram synchronous dram column address strobe the sdcas /gpio39 active low pin provides a seamless interface to cas input on synchronous dram. synchronous dram write the sdwe /gpio38 active-low pin is asserted to signify that a sdram write cycle is underway. this pin outputs logic ?1? during read bus cycles. synchronous dram chip enable the sd_cs0 /gpio60 active-low output signal is used during synchronous mode to route directly to the chip select of a sdram device. synchronous dram udqm and lqdm signals the dram byte enables udmq and ldqm are driven by the sdudqm/gpo53 and sdldqm/gpo52 byte enable outputs. synchronous dram clock the dram clock is driven by the bclk/gpio40 signal synchronous dram clock enable the bclke active high outp ut signal is used during synchronous mode to route directly to the scke signal of external sdrams. this signal provides the clock enable to the sdram.
scf5250 data sheet: technical data , rev. 1.3 14 freescale semiconductor 3.4 chip selects there are three chip select out puts on the scf5250 device. cs0 /cs4 and cs1 /qspi_cs3/gpio28 and cs2 which is associated with the ide interface read and write strobes - ide-dior and ide-diow. cs0 and cs4 are multiplexed. the scf5250 has th e option to boot from an internal boot rom. the function of the cs0/cs4 pin is determined by the boot mode. when the device is booted from internal rom, the internal rom is accessed with cs0 (requi red for boot) and the cs0/cs4 pin is driven by cs4. when the device is booted from external rom / flash, the cs0/cs4 pin is driven by cs0 and the internal rom is disabled. the active low chip sel ects can be used to access asynchronous memories. the interface is glueless. 3.5 isa bus the scf5250 supports an isa bus. using the isa bu s protocol, reads and writes for one isa bus peripheral is possible. ide-dior/ gpio31 and ide-diow /gpio32 are the read and write strobe. the peripheral can insert wait st ates by pulling ide-iordy/gpio33. cs2 is associated with th e ide-dior and ide-diow. 3.6 bus buffer signals as the scf5250 has a complicated slave bus, whic h allows sdram, asynchronous memories, and isa peripherals on the bus, it may become necessary to in troduce a buffer on the bus in certain applications. the scf5250 has a glueless interface to steer thes e bus buffers with two bus buffer output signals bufenb1 /gpio29 and bufenb2 /gpio30. 3.7 i 2 c module signals there are two i 2 c interfaces on this device as described in table 4 . the i 2 c module acts as a two-wire, bidi rectional serial interface be tween the scf5250 processor and peripherals with an i 2 c interface (e.g., led controller, a-to-d converter, d-to-a converter). when devices connected to the i 2 c bus drive the bus, they will either driv e logic-0 or high-im pedance. this can be accomplished with an open-drain output. table 4. i 2 c module signals i 2 c module signal description i 2 c serial clock the scl0/sdata1_bs1/gpio41 and scl1/txd1/gp io10 bidirectional signals are the clock signal for first and second i 2 c module operation. the i 2 c module controls this signa l when the bus is in master mode; all i 2 c devices drive this signal to synchronize i 2 c timing. signals are multiplexed i 2 c serial data the sda0/sdata3/gpio42 and sda1/rxd1/gpio44 bidirectional signals are the data input/output for the first and second serial i 2 c interface. signals are multiplexed
scf5250 data sheet: technical data , rev. 1.3 freescale semiconductor 15 3.8 serial module signals the signals described in table 5 transfer serial data between the two uart modules and the external peripherals. 3.9 timer module signals table 6 describes the timer module signal which pr ovides an external interface to timer0. table 5. serial module signals serial module signal description receive data the rxd0/gpio46 and sda1/rxd1/gpio44 are the inputs on which serial data is received by the duart. data is sampled on rxd[1:0] on the risi ng edge of the serial clock source, with the least significant bit received first. transmit data the duart transmits serial data on the txd0/gpio45 and scl1/txd1/gpi o10 output signals. data is transmitted on the falling edge of the serial clock s ource, with the least significant bit transmitted (lsb) first. when no data is being transmitted or the transmi tter is disabled, these two signals are held high. txd[1:0] are also held high in local loopback mode. request to send the ddata3/rts0/gp104 and ddata1/rts1/ sdata2_bs2/gpio2 request-to-send outputs indicate to the peripheral device that the duart is ready to send data and requires a clear-to-send signal to initiate transfer. clear to send peripherals drive the ddata2/c ts0/gpio3 and ddata0/cts1/sdata0_sdio1/gpio1 inputs to indicate to the scf5250 serial module that it can begin data transmission. table 6. timer module signals serial module signal description timer output the sdatao1/tout0/gpio18 programmable output pulse or toggle on various timer events.
scf5250 data sheet: technical data , rev. 1.3 16 freescale semiconductor 3.10 serial audio interface signals table 7 describes the signals that provide the external audio interface. 3.11 digital audio interface signals table 8 describes the signals for the digital audio interface. table 7. serial audio interface signals serial module signal description serial audio bit clock the sclk1/gpio 20, sclk2/gpio22 and sclk3/gpio35, multiplexed pins can serve as general purpose i/os or serial audio bit clocks. as bit clocks, these bidirectional pins can be programmed as outputs to drive their associated serial audio (iis) bit clocks. alternately, these pins can be programmed as inputs when the serial audio bit clocks are driven internally. the functionality is programmed within the audio module. during reset, these pins are configured as input serial audio bit clocks. serial audio word clock the lrck1/gpio19, lrck2/gpio 23 and lrck3/gpio43/audio_clock multiplexed pins can serve as general purpose i/os or serial audio word clocks. as word clocks, the bidirectional pins can be programmed as inputs to drive their associated se rial audio word clock. alternately, these pins can be programmed as outputs when the serial audio word clocks are derived internally. the functionality is programmed within the audio module. during reset, these pins are configured as input serial audio word clocks. lrck3/gpio43/audio_clock can be used as the external audio clock input. if the core clock chosen to be non-audio specific. serial audio data in the sdatai1/gpio17 and sdatai3/gpio 8 multiplexed pins can serve as general purpose i/os or serial audio inputs. as serial audio inputs the data is sent to interfaces 1and 3 respectively. during reset, the pins are configured as serial data inputs. serial audio data out sdato1/tout0/gpio18 and sdatao2/gp io34 multiplexed pins can serve as general purpose i/os or serial audio outputs. during reset, the pins are configured as serial data outputs. serial audio error flag the ef/gpio6 multiplexed pin can serv e as general purpose i/os or error flag input. as error flag input, this pin will input the error flag delivered by the cd-dsp. ef/gpio6 is on ly relevant for serial interface sdatai1. serial audio cflg the cflg/gpio5 multiplexed pin can serv e as general purpose i/o or cflg input. as cflg input, the pin will input the cflg flag delivered by the cd-dsp. cflg/gpio5 is only relevant for serial interface sdatai1. table 8. digital audio interface signals serial module signal description digital audio in the ebuin1/gpio36, ebuin2/s clk_out/gpio13, ebuin3/cmd_sdio2/gpio14, and qspi_cs0/ebuin4/gpio15 multiplexed signals can serve as general purpose input or can be driven by various digital audio (iec958) input sources. both functions are always active. input chosen for iec958 receiver is programmed within the audio module. input value on the 4 pins can always be read from the appropriate gpio register. digital audio out the ebuout1/gpio37 and qspi_cs1/ebu out2/gpio16 multiplexed pins can serve as general purpose i/o or as digital audio (iec958) output. ebuout1 is digital audio out for consumer mode, ebuout2 is digital audio out for professional mode. during reset, the pin is configured as a digital audio output.
scf5250 data sheet: technical data , rev. 1.3 freescale semiconductor 17 3.12 subcode interface there is a 3-line subcode interface on the scf5250 proc essor. this 3-line subcode interface allows the device to format and transm it subcode in eiaj format to a cd ch annel encoder device. the three signals are described in table 9 . 3.13 analog to digital converter (adc) the adout signal on the adout/sclk4/gpio58 pin pr ovides the reference vo ltage in pwm format. this output requires an external integr ator circuit (resistor/capac itor) to convert it to a dc level to be input to the adref pin. the six ad inputs are each fed to their own comparat or. the reference input to each (adref) is then multiplexed as only one ad comparis on can be made at any one time. note to use the adinx as general purpose inputs (r ather than there analogue function) it is necessary to generate a fixed comparator voltage level of vdd/2. this can be accomplished by a potential divider network connected to the adref pin. however in portable applications where st and-by power consumption is important the current taken by the divider network (in sta nd-by mode) could be excessive. therefore it is possible to generate a vdd/2 voltage by se lecting sclk4 output mode a nd feeding this clock signal (which is 50% duty cycle) thr ough an external integration circ uit. this would generate a voltage level equal to vdd/2 but would be disabled when stand- by mode was selected. 3.14 secure digital/memory stick card interface the device has a versatile flash car d interface that supports both secure digital and memory stick cards. the interface can either s upport one secure digital or two memory stick cards. no mixing of card types is possible. table 10 gives the pin descriptions. table 9. subcode interface signal signal name description rck/qspi_din/qspi_dout/gpio26 subcode clock input. when pin is used as subcode clock, this pin is driven by the cd channel encoder. qspi_dout/sfsy/gpio27 subcode sync output this signal is driven high if a subcode sync needs to be inserted in the efm stream. qspi_clk/subr/gpio25 subcode data output this signal is a subcode data out pin. table 10. flash memory card signals flash memory signal description ebuin2/sclkout/gpio13 clock out for both memory stick interfaces and for secure digital ebuin3/cmd_sdio2/gpio14 secure digital command line memory stick interface 2 data i/o
scf5250 data sheet: technical data , rev. 1.3 18 freescale semiconductor 3.15 queued serial peripheral interface (qspi) the qspi interface is a high-speed serial interface allowing transmit and recei ve of serial data. pin descriptions are given in table 11 . 3.16 crystal trim the xtrim/gpio0 output produces a pulse-density modulated phase/frequency difference signal to be used after low-pass filtering to control varicap-voltage to control cr ystal oscillation frequency. this will lock the crystal to the incoming digital audio signal. 3.17 clock out the mclk1/gpio11 and qspi_cs2/mclk2/gpio 24 can serve as dac clock outputs. when programmed as dac clock outputs, thes e signals are directly derived from the crystal osci llator or clock input (crin). ddatao/cts1 /sdata0_sdio1/gpio1 secure dig ital serial data bit 0 memory stick interface 1 data i/o scl0/sdata1_bs1/gpio41 secure digital serial data bit 1 memory stick interface 1 strobe ddata1/rts1 /sdata2_bs2/gpio2 secure dig ital serial data bit 2 memory stick interface 2 strobe reset output signal selection between reset function and sdata2_bs2 is done by programming pllcr register. sda0/sdata3/gpio42 secure digital serial data bit 3 table 11. queued serial peripheral interface (qspi) signals serial module signal description qspiclk/subr/gpio25 multiplexed signal iic interface cl ock or qspi clock output function select is done via pllcr register. rck/qspidin/qspi_dout/gpio26 multiplexed signal iic interface data or qspi data input. function select is done via pllcr register. rck/qspi_din/qspi_dout/gpio26 qspi_dout/sfsy/gpio27 qspi data output. qspics0/ebuin4gpio15 4 different qspi chip selects. qspics1/ebuout2/gpio16 qspics2/mclk2/gpio24 cs1/qspics3/gpio28 table 10. flash memory card signals (continued) flash memory signal description
scf5250 data sheet: technical data , rev. 1.3 freescale semiconductor 19 3.18 debug and test signals these signals interface with external i/o to provide processor debug and status signals. 3.18.1 test mode the test[2:0] inputs are used for various manufactur ing and debug tests. for normal mode test [2:1] should be ways be tied low. tes t0 should be set high for bdm debug mode and set low for jtag mode. 3.18.2 high impedance the assertion of hi_z will force all output drivers to a hi gh-impedance state. the timing on hi_z is independent of the clock. note jtag operation will override the hi_z pin. 3.18.3 processor clock output the internal pll generates this pstclk/gpio51 and out put signal, and is the pr ocessor clock output that is used as the timing reference for the de bug bus timing (ddata[3:0] and pst[3:0]). the pstclk/gpio51 is at the same fre quency as the core processor. 3.18.4 debug data the debug data pins, ddata0/cts1/sdata0_sdi o1/gpio1, ddata1/rts1/sdata2_bs2/gpio2, ddata2/cts0/gpio3, and ddata3/rts0/gpio4, are four bits wide. this nibbl e-wide bus displays captured processor data and break-point status. 3.18.5 processor status the processor status pins, pst0/gpio50, pst1/gpio49, pst2/intmon/gpio48, and pst3/intmon/gpio47, indicate the scf5250 processor status. during debug mode, the timing is synchronous with the processor clock (pstclk) and the status is not re lated to the current bus transfer. table 12 shows the encodings of these signals.
scf5250 data sheet: technical data , rev. 1.3 20 freescale semiconductor . 3.19 bdm/jtag signals the scf5250 complies with the ieee 1149.1a jtag testing standard. th e jtag test pins are multiplexed with background debug pins. 3.20 clock and reset signals the clock and reset signals configure the scf5250 pro cessor and provide interface signals to the external system. 3.20.1 reset in asserting rsti causes the scf5250scf5250 to enter reset exception processing. when rsti is recognized, the data bus is tri-stated. table 12. processor status signal encodings pst[3:0] definition (hex) (binary) $0 0000 continue execution $1 0001 begin execution of an instruction $2 0010 reserved $3 0011 entry into user-mode $4 0100 begin execution of pulse and wddata instructions $5 0101 begin execution of taken branch or synch_pc 1 1 rev. b enhancement. $6 0110 reserved $7 0111 begin execution of rte instruction $8 1000 begin 1-byte data transfer on ddata $9 1001 begin 2-byte data transfer on ddata $a 1010 begin 3-byte data transfer on ddata $b 1011 begin 4-byte data transfer on ddata $c 1100 exception processing 2 2 these encodings are asserted for multiple cycles. $d 1101 emulator mode entry exception processing 2 $e 1110 processor is stopped, waiting for interrupt 2 $f 1111 processor is halted 2
scf5250 data sheet: technical data , rev. 1.3 freescale semiconductor 21 3.20.2 clock input scf5250 includes an on-chip crystal oscillator. th e crystal should be conne cted between crin and crout. an externally generated clock signal can also be used and should be c onnected directly to the crin pin. 3.21 wake-up signal to exit power down mode, apply a low level to the wake_up/gpio21 input pin. 3.22 on-chip linear regulator the scf5250 includes an on-chip linear regulator. th is regulator provides an 1.2 v output which is intended to be used to power the scf5250 core. three pins are associat ed with this function. linin, linout and lingnd. typica lly linin would be fed by the i/o (pad) supply (3.3 v) with separate filtering recommende d to provide some isolation between the i/o and the core. in portable solutions this linear re gulator may not be efficient enough and in this case we would expect the 1.2 v supply to be generated externally, po ssibly by a highly effici ent dc-dc convertor. if not used leave pins not connected. 4 electrical characteristics table 14 through table 19 provide the electrical characteristics for the scf5250 processor. the remaining figures and tables in this secti on provide the timing di agrams and the timing pa rameters for the scf5250 processor. table 13. quick reference for electrical characteristics for see maximum ratings table 14 on page 22 operating temperature table 15 on page 22 recommended operating supply voltages table 16 on page 22 linear regulator operating specification table 17 on page 23 dc electrical specifications table 18 on page 23 operating parameters for adc dc electrical characteristics table 19 on page 24
scf5250 data sheet: technical data , rev. 1.3 22 freescale semiconductor table 15 provides the recommended operating te mperatures for the scf5250 processor. table 16 provides the recommended operating supp ly voltages for the scf5250 processor. table 14. maximum ratings rating symbol value units supply core voltage v cc -0.5 to +2.5 v maximum core operating voltage v cc +1.32 v minimum core operating voltage v cc +1.08 v supply i/o voltage v cc -0.5 to +4.6 v maximum i/o operating voltage v cc +3.6 v minimum i/o operating voltage v cc +3.0 v input voltage v in -0.5 to +6.0 v storage temperature range t stg -65 to150 o c table 15. operating temperature characteristic symbol value units maximum operating ambient temperature t amax 85 1 1 this published maximum operating ambient te mperature should be used only as a syst em design guideline. all device operating parameters are guaranteed only when the junction temperature does not exceed 105 c. c minimum operating ambient temperature t amin -40 o c table 16. recommended operating supply voltages pin name min typ max core-vdd 1.08v 1.2v 1.32v core-vss ? gnd ? pad-vdd 3.0v 3.3v 3.6v pad-vss ? gnd ? advdd 3.0v 3.3v 3.6v adgnd ? gnd ? oscpad-vdd 3.0v 3.3v 3.6v oscpad-gnd ? gnd ? pllcore1vdd 1.08v 1.2v 1.32v pllcore1gnd ? gnd ? pllcore2vdd 1.08v 1.2v 1.32v pllcore2gnd ? gnd ? lin 3.0v 3.3v 3.6v
scf5250 data sheet: technical data , rev. 1.3 freescale semiconductor 23 table 17 provides the linear regulat or operating specifications for the scf5250 processor. table 18 provides the dc electrical specifications. table 17. linear regulator 1 operating specification 1 a pmos regulator is employed as a current source in this linear regulator, so a 10f capacitor (esr 0 ... 5 ohm) is needed on t he output pin (linout) to integrate the current. typically this will require the use of a tantalum type capacitor. characteristic symbol min typ max input voltage vin 3.0v 3.3v 3.6 output voltage (lin out) vout 1.14v 1.2v 1.26v output current iout ? 100ma 150ma power dissipation pd ? ? 436uw load regulation (10% iout 90% iout) ? 40mv 50mv 60mv power supply rejection psrr ? 40db ? table 18. dc electrical specifications (i/o vcc = 3.3 vdc + 0.3 vdc) characteristic symbol min max units operation voltage range for i/o v cc 3.0 3.6 v input high voltage v ih 25.5 v input low voltage v il -0.3 0.8 v input leakage current @ 0.0 v /3.3 v during normal operation i in ? 1 a hi-impedance (three-state) leakage current @ 0.0 v/3.3 v during normal operation i tsi ? 1 a output high voltage i oh = 8ma 1 , 4ma 2 , 2ma 3 v oh 2.4 ? v output low voltage i ol = 8ma 1 , 4ma 2 , 2ma 3 v ol ?0.4 v schmitt trigger low to high threshold point 6 v t+ 1.47 ? v schmitt trigger high to low threshold point 6 v t- ?.95 v load capacitance (data[31:16], sclk[4:1], sclkout, ebuout[2:1], lrck[3:1], sdatao[2:1], cflg, ef, ddata[3:0], pst[3:0], pstclk, ide-dior, ide-diow, iordy) c l ?50 pf load capacitance (addr[24:9], bclk) c l ?40 pf load capacitance (bclke, sdcas, sdras, sdldqm, sd_cs0, sdudqm, sdwe, bufenb[2:1]) c l ?30 pf load capacitance (sda0, sda1, scl0, scl1, cmd_sdio2, sdata2_bs2, sdata1_bs1, sdata0_sdio1, cs0/cs4, cs1, oe, r/w , ta, txd[1: 0], xtrim, tdo/dso, rck, sfsy, subr, sdata3, tout0, qspid_out, qspics[3:0], gp[6:5]) c l ?20 pf
scf5250 data sheet: technical data , rev. 1.3 24 freescale semiconductor table 19 provides the operating parameters for the adc dc electrical characteristics. figure 2 and table 20 provide the clock timing di agram and timing parameters. figure 2. clock timing definition capacitance 5 , v in = 0 v, f = 1 mhz c in ?6 pf data[31:16], addr[24:9], pstclk, bclk scl, sda, pst[3:0], dd ata[3:0], tdso, sdras , sdcas , sdwe , sd_cs 0, sdldqm , sdudqm, r/w tout0, rts[1:0], tx d[1:0], sclk[4:1] bkpt /tms, dsi/tdi, dsclk/trst capacitance c in is periodically sampled rather than 100% tested. sclk[4:1], scl0, scl1, sda0, sda1, crin, rsti table 19. operating parameters for adc dc electrical characteristics characteristic symbol min typ max units operation voltage range for adc advdd 3 ? 3.6 v common mode rejection cmr 0 ? advdd?1.1 v reference voltage (external) adref 0 ? advdd?1.1 v input offset voltage v offset ?10 ? mv input hysteresis (adinx = advdd/2) v hyst 0.73 0.78 0.85 mv adc input linear operating range adinx 0 ? advdd?1.1 v table 18. dc electrical specifications (i/o vcc = 3.3 vdc + 0.3 vdc) (continued) characteristic symbol min max units crin pstclk bclk c6 c6 c7 c8 c8 c5
scf5250 data sheet: technical data , rev. 1.3 freescale semiconductor 25 note the signals shown in figure 2 are in relation to the clock. no relationship between signals is implied or intended. table 20. clock timing specification num characteris tic min max units ? crin frequency 1 1 there are only three choices for the valid audio frequencies 11.29 mhz, 16.93 mhz, or 33.86 mhz; no other values are allowed. the system clock is derived from one of these crystals via an internal pll. 5.00 33.86 mhz c5 pstclk cycle time 7.1 ? ns c6 pstclk duty cycle 40 60 % c7 bclk cycle time 14.2 ? ns c8 bclk duty cycle 45 55 %
scf5250 data sheet: technical data , rev. 1.3 26 freescale semiconductor figure 3 and figure 4 provide the input and output ac timing definition diagrams and table 21 and table 22 provide the input and out put ac timing parameters. figure 3. input/outpu t timing definition-i bclk addr[24:0] r/w data[31:16] b10 b2 b5 b10 b11 b12 s0 s1 s2 s3 s4 s5 s0 s1 s2 s3 s4 s5
scf5250 data sheet: technical data , rev. 1.3 freescale semiconductor 27 figure 4. input/output ac timing definition-iii table 21. input ac timing specification num characteristic min max units b1 1,2 1 inputs (rising): data[31:16] 2 ac timing specs assume 40pf load capacitance on bclk and 50pf load capacitanc e on output pins. if this value is different, the input and output timing specifications w ould need to be adjusted to match the clock load. signal valid to bclk rising (setup) 3 ? ns b2 1 bclk rising to signal invalid (hold) 2 ? ns b3 1 bclk to input high impedance ? 5 bclk cycle table 22. output ac timing specification num characteristic 1 min max units b10 2 bclk (8ma) rising to signal valid ? 10 ns b11 2 bclk (8ma) rising to signal invalid (hold) 3.5 ? ns b10 3 bclk (4ma) rising to signal valid ? 11 ns b11 3 bclk (4ma) rising to signal invalid (hold) 4 ? ns b12 4 bclk to high impedance (three-state) ? 14 ns b13 b14 bclk h1 h2 hiz outputs outputs bclk b3 b4 inputs
scf5250 data sheet: technical data , rev. 1.3 28 freescale semiconductor figure 5 and table 23 provide the timing diagram and ti ming parameters for the debug ac. figure 5. debug ac timing definition diagram h1 hiz to high impedance ? tbd ns h2 hiz to low impedance ? tbd ns 1 ac timing specs assume 40pf load capacitance on bclk and a 50pf load capacitance on output pins. if this value is different, the input and output timing specifications w ould need to be adjusted to match the clock load. 2 outputs (8ma): data[31:16], addr[25,23:9] 3 outputs (4ma): sdras, sdcas, sdwe, sd_cs0, sdudqm, sdldqm, bclke 4 high impedance (three-state): data[31:16] table 23. debug ac timing specification 1 1 ac timing specs assume 50pf load capa citance on pstclk and output pins. if th is value is different, the input and output timing specifications would need to be adjusted to match the clock load. num characteristic min max units d1 pstclk to signal valid (output valid) ? 6 ns d2 pstclk to signal invalid (output hold) 1.8 ? ns d3 2 2 dsclk and dsi are internally synchronized. this setup time must be met only if recognition on a particular clock is required. signal valid to pstclk (input setup) 3 ? ns d4 pstclk to signal invalid (input hold) 5 ? ns table 22. output ac timing specification (continued) num characteristic 1 min max units pstclk dsclk dsi pst[3:0] ddata[3:0] dso d3 d1 d2 d3 d4 d4
scf5250 data sheet: technical data , rev. 1.3 freescale semiconductor 29 figure 6 and table 24 provide the timing diagram and timi ng parameters for the timer module. figure 6. timer module ac ti ming definition diagram table 24. timer module ac timing specification num characteris tic min max units t1 tin cycle time 3t ? bus clocks t2 tin valid to bclk (input setup) 6 ? ns t3 bclk to tin invalid (input hold) 0 ? ns t4 bclk to tout valid (output valid) ? 10 ns t5 bclk to tout invalid (output hold) tbd ? ns t6 tin pulse width 1t ? bus clocks t7 tout pulse width 1t ? bus clocks bclk t6 t2 t3 t1 t7 t4 t5 tin tin tout
scf5250 data sheet: technical data , rev. 1.3 30 freescale semiconductor figure 7 and table 25 provide the timing diagram and timi ng parameters for the uart module. figure 7. uart module ac timing definition diagram table 25. uart module ac timing specifications num characteristic min max units u1 rxd valid to bclk (input setup) 6 ? ns u2 bclk to rxd invalid (input hold) 0 ? ns u3 cts valid to bclk (input setup) 6 ? ns u4 bclk to cts invalid (input hold) 0 ? ns u5 bclk to txd valid (output valid) ? tbd ns u6 bclk to txd invalid (output hold) 3 ? ns u7 bclk to rts valid (output valid) ? tbd ns u8 bclk to rts invalid (output hold) 3 ? ns bclk rxd cts txd rts u1 u2 u3 u4 u5 u6 u7 u8
scf5250 data sheet: technical data , rev. 1.3 freescale semiconductor 31 figure 8 provides the i2c-bus input and output timing diagram and table 26 and table 27 provide the i2c-bus input and output timing parameters. figure 8. i2c-bus input/output timing definition diagram table 26. i2c-bus input timing specifications between scl and sda num characteristic min max units m1 start condition hold time 2 ? bus clocks m2 clock low period 8 ? bus clocks m3 scl/sda rise time (vil= 0.5 v to vih = 2.4 v) ? 1 msec m4 data hold time 0 ? ns m5 scl/sda fall time (vih= 2.4 v to vil = 0.5 v) ? 1 ms m6 clock high time 4 ? bus clocks m7 data setup time 0 ? ns m8 start condition setup time (for repeated start condition only) 2 ? bus clocks m9 stop condition setup time 2 ? bus clocks table 27. i2c-bus output timing specifications between scl and sda num characteristic min max units m1 1 1 output numbers are dependent on the value programmed into t he mfdr; an mfdr programmed with the maximum frequency (mfdr = 0x20) will result in minimum output timings as shown. the mbus interface is designed to scale the actual data transition time t o move it to the middle of the scl low period. the actual position is affected by the prescale and division values programmed into the mfdr; however, numbers given are the minimum values. start condition hold time 6 ? bus clocks m2 1 clock low period 10 ? bus clocks m3 2 2 since scl and sda are open-collector-type outputs, which the processo r can only actively drive low, the time required for scl o r sda to reach a high level depends on external signal capacitance and pull-up resistor values. scl/sda rise time (v il = 0.5 v to v ih = 2.4 v) note 2 note 2 msec m4 1 data hold time 7 ? bus clocks m5 3 3 specified at a nominal 20 pf load. scl/sda fall time (v ih = 2.4 v to v il = 0.5 v) ?3 ns m6 1 clock high time 10 ? bus clocks m7 1 data setup time 2 ? bus clocks m8 1 start condition setup time (for repeated start condition only) 20 ? bus clocks m9 1 stop condition setup time 10 ? bus clocks m2 m6 m1 m4 m7 m8 m9 m5 m3 scl sda
scf5250 data sheet: technical data , rev. 1.3 32 freescale semiconductor figure 9 provides the i2c-bus and syst em clock timing diagram and table 28 provides the i2c-bus output timing parameters. figure 9. i2c and system clock timing relationship table 28. i2c output bus timings num characteristic 96 mhz units min max m10 1 1 scl and sda are internally synchronized. th is setup time must be met only if reco gnition on a particular clock is required. scl, sda valid to bclk (input setup) 2 ? ns m11 bclk to scl, sda invalid (input hold) 4.5 ? ns m12 2 2 since scl and sda are open-collector-type output s, which the processor can only actively drive low, this specification applies only when scl or sda are driven low by the processor. the time required for scl or sda to reach a high level depends on external signal capac itance and pull-up resistor values. bclk to scl, sda low (output valid) ? 10 ns m13 3 3 since scl and sda are open-collector-type outputs, which the proces sor can only actively drive low, this specification applies only when scl or sda are actively being driven or held low by the processor. bclk to scl, sda invalid (output hold) 3 ? ns bclk scl, sda in scl, sda out scl, sda out m10 m11 m12 m13
scf5250 data sheet: technical data , rev. 1.3 freescale semiconductor 33 figure 10 provides the general-purpose pa rallel port timing diagram and table 29 provides the timing parameters. figure 10. general-purpose i/o port ac timing definition diagram table 29. general-purpose i/o port ac timing specifications num characteristic min max units p1 gpio valid to bclk (input setup) 6 ? ns p2 bclk to gpio invalid (input hold) 0 ? ns p3 bclk to gpio valid (output valid) ? tbd ns p4 bclk to gpio invalid (output hold) 1 ? ns bclk gpio in gpio out p1 p2 p4 p3
scf5250 data sheet: technical data , rev. 1.3 34 freescale semiconductor figure 11 provides the ieee 1149.1 jtag timing diagram and table 30 provides the timing parameters. figure 11. jtag ac timing diagram table 30. jtag ac timing specifications num characteristic min max units ? tck frequency of operation 0 10 mhz j1 tck cycle time 100 ? ns j2a tck clock pulse high width 25 ? ns j2b tck clock pulse low width 25 ? ns j3a tck fall time (v ih =2.4 v to v il =0.5 v) ? 5 ns j3b tck rise time (v il =0.5 v to v ih =2.4 v) ? 5 ns j4 tdi, tms to tck rising (input setup) 8 ? ns j5 tck rising to tdi, tms invalid (hold) 10 ? ns j6 boundary scan data valid to tck (setup) tbd ? ns j7 tck to boundary scan data invalid to rising edge (hold) tbd ? ns j8 trst pulse width (asynchronous to clock edges) 12 ? ns j9 tck falling to tdo valid (signal from driven or three-state) ? 15 ns j10 tck falling to tdo high impedance ? 15 ns j1 j2a j2b j4 j5 j6 j7 j8 j9 j10 j11 j12 j3a j3b tck tdi, tms trst tdo boundary scan data output boundary scan data input
scf5250 data sheet: technical data , rev. 1.3 freescale semiconductor 35 figure 12 provides the sclk input, sdata output timing diagram for the iis module and table 31 provides the timing parameters. figure 12. sclk input, sdata output timing diagram figure 13 provides the sclk output, sdata output timing diagram for the iis module and table 32 provides the timing parameters. figure 13. sclk output, sdata output timing diagram j11 tck falling to boundary scan data valid (signal from driven or three-state) ? tbd ns j12 tck falling to boundary scan. data high impedance ? tbd ns table 31. sclk input, sdata output timing specifications num characteris tic min max units tu sclk fall to sdatao rise ? 25 ns td sclk fall to sdatao fall ? 25 ns table 32. sclk output, sdata output timing specifications num characteris tic min max units tu sclk fall to sdatao rise ? 3 ns td sclk fall to sdatao fall ? 3 ns table 30. jtag ac timing specifications (continued) num characteristic min max units sclk (input) sdatao1, 2 (output) tu td sclk (output) sdatao1, 2 (output) tu td
scf5250 data sheet: technical data , rev. 1.3 36 freescale semiconductor figure 14 provides the sclk input/output, sdata input timing diagram and table 33 provides the timing parameters. figure 14. sclk input/output, sdata input timing diagram 5 pin-out and package information visit the url [http://www.freescale.com/coldfire ] and choose the documentation library to obtain information on the mechanical characteristics of the scf5250 integrated microprocessor. thermal characteristics are not available at this time. the scf5250 is available in a 144 pin qfp and a 196 pin mapbga package. use table 34 to find the information desired. 5.1 144 qfp pin assignments the scf5250 can be assembled in 144-pin qfp package. table 35 provides the pin assignments for the package. table 33. sclk input/output, sd ata input timing specifications num characteris tic min max units tsu sdatai in to sclkn -5 ? ns th sclk rise to sdatai 3 ? ns table 34. section quick reference for chip package see 144 pin qfp pin assignments table 35 on page 37 package drawings figure 15 on page 42 figure 16 on page 43 figure 17 on page 44 196 mapbga pin assignments table 36 on page 45 package drawings figure 18 on page 52 figure 19 on page 53 ball map figure 20 on page 54 sclk sdata1, 3, 4 (input) tsu th ( inp ut or output )
scf5250 data sheet: technical data , rev. 1.3 freescale semiconductor 37 table 35. 144 qfp pin assignments 144 qfp pin number name type description pin state after reset 01 data16 i/o data x 02 a23/gpo54 i/o sdram address / static adr out (requires pull up /down for boot-up selection) 03 pad-vdd ? ? ? 04 a22 o sdram address / static adr out 05 a21 o sdram address / static adr out 06 a20/a24 o sdram address / static adr out 07 a19 o sdram address / static adr out 08 a18 o sdram address / static adr out 09 pad-gnd ? ? ? 10 a17 o sdram address / static adr out 11 a16 o sdram address / static adr out 12 a15 o sdram address / static adr out 13 a14 o sdram address / static adr out 14 a13 o sdram address / static adr out 15 pad-vdd ? ? ? 16 a12 o sdram address / static adr out 17 a11 o sdram address / static adr out 18 core-vdd ? ? ? 19 core-gnd ? ? ? 20 a10 o sdram address / static adr out 21 a9 o sdram address / static adr out 22 a8 o sdram address / static adr out 23 a7 o sdram address / static adr out 24 a6 o sdram address / static adr out 25 a5 o sdram address / static adr out 26 pad-gnd ? pad-gnd ? 27 a4 o sdram address / static adr out 28 a3 o sdram address / static adr out 29 a2 o sdram address / static adr out 30 a1 o sdram address / static adr out 31 cs0/cs4 o static chip select 0 / static chip select 4 out
scf5250 data sheet: technical data , rev. 1.3 38 freescale semiconductor 32 rw o bus write enable out 33 osc pad vdd ? ? ? 34 crin i crystal / external clock input x 35 crout o crystal clock output x 36 osc pad gnd ? osc_pad_gnd ? 37 pll core1 vdd ? ? ? 38 pll core2 vdd ? ? ? 39 pll core2 gnd ? ? ? 40 pll core1 gnd ? ? ? 41 oe o output enable out 42 ide-diow/gpio32 i/o ide diow out / high 43 ide-iordy/gpio33 i/o ide interface iordy in / low 44 ide-dior/gpio31 i/o ide interface dior out / high 45 bufenb2/gpio30 i/o external buffer 2 enable out / high 46 bufenb1/gpio29 i/o external buffer 1 enable out / high 47 ta/gpio12 i/o transfer acknowledge in (requires pull-up for normal operation) 48 wake_up/gpio21 i/o wake-up input in (requires pull-up for normal operation) 49 ebuin2/sclk_out/ gpio13 i/o audio interfaces ebu in 2 / flashmedia clock in / low 50 ebuin3/cmd_sdio2/ gpio14 i/o audio interfaces ebu in 3 / flashmedia command interface in / low 51 pad vdd ? ? ? 52 ebuin1/gpio36 i/o audio interfaces ebu in 1 in / low 53 ebuout1/gpio37 i/o audio interfaces ebu out 1 out / low 54 xtrim/gpio0 i/o audio interfaces x-tal trim out / clock out 55 cs1/qspi_cs3/gpio28 i/o chip select 1/ qspi chip select 3 out / high 56 rck/ qspi_din/qspi_dout/ gpio26 i/o subcode rck interface / qspi data in / data out out / low 57 qspi_clk/subr/gpio25 i/o qspi clock pin / subcode interface out / low 58 qspi_dout/sfsy/ gpio27 i/o qspi data output / subcode interface sfsy out / low table 35. 144 qfp pin assignments (continued) 144 qfp pin number name type description pin state after reset
scf5250 data sheet: technical data , rev. 1.3 freescale semiconductor 39 59 qspi_cs1/ebuout2/ gpio16 i/o qspi chip select 1 output / audio interface ebu output 2 out / low 60 qspi_cs0/ebuin4/ gpio15 i/o qspi chip select 0 / audio interface ebuin 4 out / low 61 pad gnd ? ? ? 62 sclk1/gpio20 i/o audio interfaces serial clock 1 in / low 63 lrck1/gpio19 i/o audio interfaces word clock 1 in / low 64 sdatao1/tout0/ gpio18 i/o audio interfaces serial data output 1 / timer output 0 out / low 65 sdatai1/gpio17 i audio interfaces serial data in 1 in / low 66 cflg/gpio5 i/o cflg input in / low 67 ef/gpio6 i/o error flag input in / low 68 qspi_cs2/mclk2/ gpio24 i/o qspi chip select output 2 / audio master clock output 2 out / low 69 sdatai3/gpio8 i/o audio interfaces serial data input 3 in / low 70 adin0/gpi52 a ad input 0 in only 71 adin1/gpi53 a ad input 1 in only 72 adin2/gpi54 a ad input 2 in only 73 advdd ? ? ? 74 adgnd ? ? ? 75 adin3/gpi55 a ad input 3 in only 76 adin4/gpi56 a ad input 4 in only 77 adin5/gpi57 a ad input 5 in only 78 adref a adc reference input in 79 adout/sclk4/ gpio58 i/o ad output / sclk4 (f or gpi function in low power applications) out / clock output 80 lrck3/gpio43/ audio_clock i/o audio interface lrck3 / audio master clock input in / low 81 sclk3/gpio35 i/o audio interface sclk3 in / low 82 scl0/sdata1_bs1/ gpio41 i/o i2c0 clock line / flashmedia data interface out / low 83 sda0/sdata3/gpio42 i/o i2c0 data / flashmedia data interface hi-z 84 ddata0/cts1/ sdata0_sdio1/gpio1 i/o debug / uart1 cts / flashmedia data interface out / high 85 ddata1/rts1/ sdata2_bs2/gpio2 i/o debug / uart1 rts / flashmedia data interface out / high table 35. 144 qfp pin assignments (continued) 144 qfp pin number name type description pin state after reset
scf5250 data sheet: technical data , rev. 1.3 40 freescale semiconductor 86 ddata2/cts0/gpio3 i/o debug / uart0 cts out / high 87 ddata3/rts0/gpio4 i/o debug / uart0 rts out / high 88 scl1/txd1/gpio10 i/o i2c1 clock line / second uart transmit data output out / low 89 core vdd ? ? ? 90 core gnd ? ? ? 91 sda1/rxd1/gpio44 i/o i2c1 data line / second uart receive data input hi-z 92 pad vdd ? ? ? 93 txd0/gpio45 i/o first uart transmit data output out / high 94 rxd0/gpio46 i/o first uart receive data input in / low 95 pst3/intmon1/ gpio47 i/o debug / interrupt monitor output 1 out / high 96 pst2/intmon2/gpio48 i/o debug / interrupt monitor output 2 out / high 97 pad gnd ? ? ? 98 pst1/gpio49 i/o debug out / high 99 pst0/gpio50 i/o debug out / high 100 pstclk/gpio51 i/o debug out / clock output 101 tdo/dso o jtag/debug bdm 102 tdi/dsi i jtag/debug bdm 103 tck i jtag bdm 104 tms/bkpt i jtag/debug bdm 105 trst/dsclk i jtag/debug bdm 106 rsti i reset x 107 sclk2/gpio22 i/o audio interfaces serial clock 2 in / low 108 lrck2/gpio23 i/o audio interfaces ebu out 1 in /low 109 linout a linear regulator output x 110 linin a linear regulator input x 111 lingnd ? linear regulator ground x 112 sdatao2/gpio34 i/o audio interfaces serial data output 2 out / low 113 mclk1/gpio11 i/o audio master clock output 1 out / clock output 114 hi-z i jtag x 115 test2 i test x table 35. 144 qfp pin assignments (continued) 144 qfp pin number name type description pin state after reset
scf5250 data sheet: technical data , rev. 1.3 freescale semiconductor 41 116 test1 i test x 117 test0 i test x 118 sdwe/gpio38 i/o sdram write enable out / high 119 sdcas/gpio39 i/o sdram cas out / high 120 pad vdd ? ? ? 121 sdras/gpio59 i/o sdram ras out / high 122 sd_cs0/gpio60 i/o sdram chip select out 0 out / high 123 sdldqm/gpo52 o sdram ldqm out / high 124 sdudqm/gpo53 o sdram udqm out / high 125 bclke/gpio63 i/o sdram clock enable output out / high 126 bclk/gpio40 i/o sdram clock output out / high 127 data31 i/o data x 128 data30 i/o data x 129 pad gnd ? ? ? 130 data29 i/o data x 131 data28 i/o data x 132 data27 i/o data x 133 data26 i/o data x 134 data25 i/o data x 135 pad-vdd ? ? ? 136 data24 i/o data x 137 data23 i/o data x 138 data22 i/o data x 139 data21 i/o data x 140 data20 i/o data x 141 pad gnd ? ? ? 142 data19 i/o data x 143 data18 i/o data x 144 data17 i/o data x table 35. 144 qfp pin assignments (continued) 144 qfp pin number name type description pin state after reset
scf5250 data sheet: technical data , rev. 1.3 42 freescale semiconductor 5.2 144 qfp package the scf5250 is available in a 144-pin qfp package. for the 144 qfp package dr awings, refer to figure 15 on page 42, figure 16 on page 43, and figure 17 on page 44. figure 15. 144 qfp package (1 of 3)
scf5250 data sheet: technical data , rev. 1.3 freescale semiconductor 43 figure 16. 144 qfp package (2 of 3)
scf5250 data sheet: technical data , rev. 1.3 44 freescale semiconductor figure 17. 144 qfp package (3 of 3)
scf5250 data sheet: technical data , rev. 1.3 freescale semiconductor 45 5.3 196 mapbga pin assignments the scf5250 can be assembled in a 196-pin mapbga package. table 36 lists the 196 mapbga pin assignments. table 36. 196 mapbga pin assignments mapbga pin name type description pin state after reset b1 data16 i/o data x d3 a23_gpo54 i/o sdram address / static adr out (requires pull up/down for boot-up selection p_vdd pst_vdd pst_vdd c1 a22 o sdram address / static adr out d2 a21 o sdram address / static adr out e3 a20_a24 i/o sdram address / static adr out (requires pull up/down for boot-up selection d1 a19 o sdram address / static adr out e2 a18 o sdram address / static adr out p_gnd pst_gnd pst_gnd f3 a17 o sdram address / static adr out e1 a16 o sdram address / static adr out f2 a15 o sdram address / static adr out f1 a14 o sdram address / static adr out g3 a13 o sdram address / static adr out p_vdd pad_vdd pad_vdd g2 a12 o sdram address / static adr out g1 a11 o sdram address / static adr out core_vdd core_vdd core_vdd c_gnd core_vss core_vss out h2 a10 o sdram address / static adr out j1 a9 o sdram address / static adr out h3 a8 o sdram address / static adr out k1 a7 o sdram address / static adr out
scf5250 data sheet: technical data , rev. 1.3 46 freescale semiconductor j2 a6 o sdram address / static adr out l1 a5 o sdram address / static adr out p_gnd pad_gnd pad_gnd j3 a4 o sdram address / static adr out k2 a3 o sdram address / static adr out l2 a2 o sdram address / static adr out m1 a1 o sdram address / static adr out k3 cs0 o static chip select 0 out l3 rwb o bus write enable out j5 oscpad_vdd oscpad_vdd m2 crin crystal / external clock input x n1 crout crystal clock output x j6 oscpad_gnd oscpad_gnd k5 pllcore_vdd pllcore_vdd k5 pllcore_vdd pllcore_vdd k5 pllcore_vdd pllcore_vdd k6 pllcore_gnd pllcore_gnd k6 pllcore_gnd pllcore_gnd k6 pllcore_gnd pllcore_gnd m3 oe o output enable out m4 idediow_gp32 i/o ide diow out / high m5 ideiordy_gp33 i/o ide interface iordy out / low n3 idedior_gp31 i/o ide interface dior out / high m6 bufenb2_gp30 i/o external buffer 2 enable out / high p2 bufenb1_gp29 i/o external buffer 1 enable out / high n4 ta_gp12 i/o transfer acknowledge in (requires pull-up for normal operation) table 36. 196 mapbga pin assignments (continued) mapbga pin name type description pin state after reset
scf5250 data sheet: technical data , rev. 1.3 freescale semiconductor 47 n5 wakeup_gp21 i/o wake-up input in (requires pull-up for normal operation) p3 ebuin2_sclkout_gp1 3 i/o audio interfaces ebuin2 / flashmedia clock in / low p4 ebuin3_cmdsdio2_gp 14 i/o audio interfaces ebuin3 / flashmedia clock in / low p_vdd pad_vdd i/o pad_vdd n6 ebuin1_gp36 i/o audio interfaces ebuin1 in / low p5 ebuout1_gp37 i/o audio interfaces ebuout1 out / low m7 xtrim_gp0 i/o audio interfaces x-tal trim out / clock out p6 qspics3_cs1_gp28 i/o qspi chip select 3 out / high n7 rck_qspidin_qspido ut_gp26 i/o subcode rck interface / qspi data in / data out out / low p7 qspiclk_subr_gp25 i/o qspi clockp in / subcode interface out / low p8 qspidout_sfsy_gp27 i/o qspi data output / subcode interface sfsy out / low m8 qspics1_ebuout2_gp 16 i/o qspi chip select 1 output / audio interface ebu output 2 out / low n8 qspics0_ebuin4_gp15 i/o qspi ch ip select 0 output / audio interface ebuin4 out / low p_gnd pad_gnd i/o pad_gnd p9 sclk1_gp20 i/o audio interfaces serial clock 1 in / low m9 lrck1_gp19 i/o audio interfaces word clock 1 in / low n9 sdatao1_tout1_gp18 i/o audio inte rfaces serial data output 1 / timer output 1 out / low p10 sdatai1_gp17 i/o audio interfaces serial data input 1 in / low n10 cflg_gp5 i/o cflg input in / low m10 ef_gp6 i/o error flag input in / low p11 qspics2_mclk2_gp24 i/o qspi chip select output 2 / audio master clock output 2 out / low n11 sdatai3_gp8 i/o audio interfaces serial data input 3 in / low table 36. 196 mapbga pin assignments (continued) mapbga pin name type description pin state after reset
scf5250 data sheet: technical data , rev. 1.3 48 freescale semiconductor m11 adin0_gpi52 a ad input 0 in only p12 adin1_gpi53 a ad input 1 in only p13 adin2_gpi54 a ad input 2 in only n12 ad_vdd ad_vdd m13 ad_gnd ad_gnd m12 adin3_gpi55 a ad input 3 in only l12 adin4_gpi56 a ad input 4 in only k12 adin5_gpi57 a ad input 5 in only n13 adref a adc reference input in n14 adout_sclk4_gp58 i/o ad output / sclk4 (for gpi function in low power applications out / clock output l13 lrck3_gp43 i/o audio interface lrck3 in m14 sclk3_gp35 i/o audio interface sclk3 in j12 scl_sdata1bs1_gp41 i/o i2c clock line / flashmedia data interface in / low l14 sda_sdata3_gp42 i/o i2c data line / flashmedia data interface hi-z j13 ddata0_cts2b_sdata 0sdio1_gp1 i/o debug / uart2 cts / flashmedia data interface out / high k14 ddata1_rts2b_sdata 2bs2_gp2 i/o debug / uart2 rts / flashmedia data interface out / high h12 ddata2_cts1b_gp3 i/o debug / uart1 cts out / high j14 ddata3_rts1b_gp4 i/o debug / uart1 rts out / high h13 scl2_txd2_gp10 i/o i2c2 clock line / second uart transmit data output out / low core_vdd core_vdd i/o core_vdd c_gnd core_gnd i/o core_gnd h14 sda2_rxd2_gp44 i/o i2c2 data line / second uart2 receive data input hi-z p_vdd pad_vdd i/o pad_vdd g14 txd1_gp45 i/o uart1 transmit data output out / high table 36. 196 mapbga pin assignments (continued) mapbga pin name type description pin state after reset
scf5250 data sheet: technical data , rev. 1.3 freescale semiconductor 49 g13 rxd1_gp46 i/o uart1 receive data input out / low g12 pst3_intmon1_gp47 i/o debug / interrupt monitor output 1 out / high f12 pst2_intmon2_gp48 i/o debug / interrupt monitor output 2 out / high p_gnd pad_gnd i/o pad_gnd f14 pst1_gp49 i/o debug out / high f13 pst0_gp50 i/o debug out / high e14 pstclk_gp51 i/o debu g out / clock output e13 tdo_dso o jtag / debug bdm d13 tdi_dsi i jtag / debug bdm e12 tck i jtag bdm c13 tms_bkpt i jtag / debug bdm d12 trst_dsclk i jtag / debug bdm d14 rsti i reset x c14 sclk2_gp22 i/o audio interfaces serial clock 2 in / low b14 lrck2_gp23 i/o audio interfaces word clock 2 in / low c11 linout a linear regulator output x c11 linout a linear regulator output x b12 linin a linear regulator input x b12 linin a linear regulator input x p_gnd lin_gnd linear regulator ground x c10 sdatao2_gp34 i/o audio interfaces serial data output 2 out / low a12 mclk1_gp11 i/o audio master clock output 1 out / clock output --- vbgt b11 hiz_b i jtag x b10 test2 i test x c9 test1 i test x a11 test0 i test x table 36. 196 mapbga pin assignments (continued) mapbga pin name type description pin state after reset
scf5250 data sheet: technical data , rev. 1.3 50 freescale semiconductor b9 sdwe_gp38 i/o sdram write enable out / high a10 sdcas_gp39 i/o sdra cas out / high p_vdd pad_vdd pad_vdd out / high c8 sdras_gp59 i/o sdram ras out / high a9 sdcs0_gp60 i/o sdram chip select out 0 out / high b8 sdldqm_gpo52 o sdram ldqm out / high a8 sdudqm_gpo53 o sdram udqm out / high a7 bclke_gpo63 o sdram clock enable output out / high a6 bclk_gp40 i/o sdram clock output out / high b7 data31 i/o data x a5 data30 i/o data x p_gnd pad_gnd i/o pad_gnd c7 data29 i/o data x b6 data28 i/o data x a4 data27 i/o data x b5 data26 i/o data x c6 data25 i/o data x p_vdd pad_vdd i/o pad_vdd b4 data24 i/o data x b3 data23 i/o data x c5 data22 i/o data x a2 data21 i/o data x b2 data20 i/o data x p_gnd pad_gnd i/o pad_gnd c4 data19 i/o data x c3 data18 i/o data x c2 data17 i/o data x table 36. 196 mapbga pin assignments (continued) mapbga pin name type description pin state after reset
scf5250 data sheet: technical data , rev. 1.3 freescale semiconductor 51 5.4 196 mapbga package and ball map the scf5250 is available in a 196-pin mapbga p ackage. for the 196 mapbga package drawings, refer to figure 18 on page 52 and figure 19 on page 53. for the 196 mapbga ball map, refer to figure 20 on page 54. a1 bga1_nc_a1 nc a14 bga1_nc_a14 nc p1 bga1_nc_p1 nc p14 bga1_nc_p14 nc table 36. 196 mapbga pin assignments (continued) mapbga pin name type description pin state after reset
scf5250 data sheet: technical data , rev. 1.3 52 freescale semiconductor figure 18. 196 mapbga package (1 of 2)
scf5250 data sheet: technical data , rev. 1.3 freescale semiconductor 53 figure 19. 196 mapbga package (2 of 2)
scf5250 data sheet: technical data , rev. 1.3 54 freescale semiconductor figure 20. 196 mapbga ball map 1234567891011121314 a bga1_nc_a1 data21 p_vdd data27 data30 bclk_gp40 bclke_gpo6 3 sdudqm_gp o53 sdcs0_gp60 sdcas_gp39 test0 mclk1_gp11 p_vdd bga1_nc_a14 b data16 data20 data23 data24 data26 data28 data31 sdldqm_gpo 52 sdwe_gp38 test2 hiz_b linin p_vdd lrck2_gp23 c a22 data17 data18 data19 data22 data25 data29 sdras_gp59 test1 sdatao2_gp 34 linout p_vdd tms_bkpt sclk2_gp22 d a19 a21 a23_gpo54 p_vdd p_vdd p_vdd p_vdd p_vdd p_vdd p_gnd p_vdd trst_dsclk tdi_dsi rsti e a16 a18 a20_a24 p_vdd p_vdd p_gnd p_gnd p_gnd p_gnd p_vdd p_vdd tck tdo_dso pstclk_gp51 f a14 a15 a17 p_vdd p_gnd p_gnd p_gnd p_gnd p_gnd p_vdd p_vdd pst2_intmon 2_gp48 pst0_gp50 pst1_gp49 g a11 a12 a13 p_vdd p_vdd p_vdd p_vdd p_gnd p_gnd core_vdd p_vdd pst3_intmon 1_gp47 rxd1_gp46 txd1_gp45 h core_vdd a10 a8 core_vdd core_vdd p_gnd c_gnd c_gnd c_gnd core_vdd core_vdd ddata2_cts1 b_gp3 scl2_txd2_g p10 sda2_rxd2_ gp44 j a9 a6 a4 core_vdd oscpad_vdd oscpad_gnd p_gnd p_gnd p_gnd p_gnd p_gnd scl_sdata1 bs1_gp41 ddata0_cts2 b_sdata0sdi o1_gp1 ddata3_rts1 b_gp4 k a7 a3 cs0 p_gnd pllcore_vd d pllcore_gn d p_gnd p_gnd p_gnd p_gnd p_gnd adin5_gpi57 p_gnd ddata1_rts2 b_sdata2bs2 _gp2 l a5 a2 rwb p_gnd p_gnd p_gnd p_vdd p_vdd p_gnd p_gnd p_gnd adin4_gpi56 lrck3_gp43 sda_sdata3 _gp42 ma1crinoe idediow_gp3 2 ideiordy_gp 33 bufenb2_gp 30 xtrim_gp0 qspics1_ebu out2_gp16 lrck1_gp19 ef_gp6 adin0_gpi52 adin3_gpi55 ad_gnd sclk3_gp35 n crout p_gnd idedior_gp3 1 ta_gp12 wakeup_gp2 1 ebuin1_gp36 rck_qspidin _qspidout_ gp26 qspics0_ebu in4_gp15 sdatao1_to ut1_gp18 cflg_gp5 sdatai3_gp8 ad_vdd adref adout_sclk 4_gp58 p bga1_nc_p1 bufenb1_gp 29 ebuin2_sclk out_gp13 ebuin3_cmd sdio2_gp14 ebuout1_gp 37 qspics3_cs1 _gp28 qspiclk_sub r_gp25 qspidout_s fsy_gp27 sclk1_gp20 sdatai1_gp1 7 qspics2_mcl k2_gp24 adin1_gpi53 adin2_gpi54 bga1_nc_p14
scf5250 data sheet: technical data , rev. 1.3 freescale semiconductor 55 6 product documentation this section contains this document?s revision histor y and the reference documents that are available to provide more information about the scf5250 processor. 6.1 reference documents the following list contains the documents that pr ovide a complete description of the scf5250 and are required to design properly with the part. the doc uments are available at: http://www.freescale.com. coldfire family programmer?s reference manual (order number cfprm) version 2/2m coldfire core processor user?s manual (order number coldfire2um) version 2/2m coldfire core processor user?s manual addendum (order number coldfire2umad) scf5250 user?s manual (order number scf5250um) 6.2 revision history table 37 list the revision history for this data sheet. table 37. revision history revision description 1.3 added 144 lqfp package drawings. added 196 mapbga package drawings, pin assignments, and ball map. 1.2 added scf5250dag120 and scf5250eag120 parts in ta b l e 1 . content has been reorganized, however there are no other content removal or additions.
document number: scf5250ec rev. 1.3 07/2006 how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064, japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only : freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-521-6274 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circui ts or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpos e, nor does freescale semiconductor assume any liability arising out of the application or use of any product or ci rcuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor dat a sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2006. all rights reserved.

▲Up To Search▲

Price & Availability of SCF5250DAG1201

	To Download SCF5250DAG1201 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .